merge_and_store, chain_link
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@ -99,25 +99,19 @@ Mark II
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% Build and write the new list cell.
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incr(SP),
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sub_base_from_offset(TEMP2, SP),
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sub_base_from_offset(TEMP0, SP)
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]),[
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lsl_imm(TEMP2, TEMP2, 15), % TEMP2 := TEMP2 << 15
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ior(TEMP2, TEMP2, TEMP0),
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store_word(TEMP2, SP, 0)
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],⟐([
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sub_base_from_offset(TEMP0, SP),
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merge_and_store(TEMP2, TEMP0, SP),
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incr(SP),
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sub_base_from_offset(TEMP3, SP)
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sub_base_from_offset(TEMP3, SP),
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chain_link(TOS, TEMP3),
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jump(Done) % Rely on mainloop::Done to write TOS to RAM.
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]),[
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mov_imm_with_shift(TOS, 2), % TOS := 4 << 15
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ior(TOS, TOS, TEMP3),
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do_offset(Done), % Rely on mainloop::Done to write TOS to RAM.
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label(Expression),
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expr_cell(ConsSym, 0),
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label(ConsSym), symbol(Cons)
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].
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/*
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This stage ⟐//1 converts the intermediate representation to assembly
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@ -152,6 +146,8 @@ language.
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⟐(label(L)) --> [label(L)]. % Pass through.
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⟐(jump(To)) --> [do_offset(To)]. % Pass through.
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⟐(incr(SP)) --> [sub_imm(SP, SP, 4)]. % SP -= 1 (word, not byte).
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⟐(if_literal(TERM, Push, TEMP)) -->
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@ -167,6 +163,15 @@ language.
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and(TEMP, TEMP, TERM),
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do(TEMP)]. % Jump to command.
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⟐(merge_and_store(HeadAddr, TailAddr, SP)) -->
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[lsl_imm(HeadAddr, HeadAddr, 15), % HeadAddr := HeadAddr << 15
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ior(HeadAddr, HeadAddr, TailAddr),
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store_word(HeadAddr, SP, 0)].
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⟐(chain_link(In, Term)) -->
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[mov_imm_with_shift(In, 2), % In := 4 << 15
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ior(In, In, Term)].
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do :-
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compile_program(Binary),
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